In semiconductor integrated circuit devices barrier layers are used to avoid atomic diffusion of various elements from one layer to another. For example, barrier layers are used in conjunction with conductive materials, such as those used as interconnect devices or wiring layers. The conductive materials are generally isolated from other features of semiconductor integrated circuit devices by a dielectric material.
In damascene processing, the interconnect structure or wiring pattern is formed within grooves or other openings formed within a dielectric film. Using known techniques a photoresist material is used to define the wiring pattern. The patterned photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. The etched openings are used to define wiring patterns in the dielectric layer. These wiring patterns can extend from one surface of the dielectric layer to the other surface of the dielectric layer. Alternatively, the wiring patterns can be confined to a single layer, that is, not extend to the opposite surface of the dielectric layer. The wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination thereof. Excess metal can then be removed by chemical mechanical polishing through a process known as planarization.
In the single damascene process, via openings are provided in the dielectric layer and filled with a conducting metal, which is often referred to as metallization, to provide electrical contact between layers of wiring levels. In the dual damascene process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with the conducting metal. The dual damascene process can simplify the manufacturing process by eliminating some internal interfaces. Damascene processing followed by metallization is continued for each layer in the electronic component until the electronic device is completed.
Barrier layers are needed between the dielectric material and the conductive material in order to prevent atoms of the conductive material from diffusing into and at times through the dielectric material and into other active circuit device structures. Diffusion of conductive material in the device can cause inter-level or intra-level shorts through the dielectric material. Also, junction leakage may result, and threshold voltage (Vt) levels of the transistors formed within the substrate can shift. In some cases, device functionality can be destroyed.
Diffusion is a particular concern when a high diffusivity element is used as a conductive material in the semiconductor structures. For example, copper atoms often exhibit relatively high diffusion mobility in most dielectric materials.—Yet, in spite of this problem, copper is a favored material for interconnects because of its superior conductivity. As a result, if copper is used as an interconnect structures, the copper needs to be confined with a barrier layer.
Barrier layers used in many BEOL integration schemes are typically deposited by physical vapor deposition (PVD). FIGS. 1A to 1C are representational cross-sectional views of process steps taken to provide a copper interconnect of the prior art. With reference to FIG. 1A, a dual-damascene copper interconnect is represented, which includes trench 14 and via 15, copper line 12, cap layer 13 (e.g. silicon nitride, silicon carbide, or silicon oxide) and interlayer dielectric 11. As shown, via 15 is etched in the interlayer dielectric 11 and the cap layer 13 to expose copper line 12. A barrier layer 16 (e.g. tantalum, tantalum nitride) is deposited on the patterned interlayer dielectric 11 using a PVD process, as shown in FIG. 1B. FIG. 1B also depicts the poor or non-conformal coverage of the PVD deposited barrier layer 16 at the lower side walls near the bottom of the via 15, e.g., at site 17 as indicated. Typically, a copper seed layer (not shown) is then deposited over the barrier layer, followed by a Cu plating process to fill the features, i.e. 14 and 15, as shown in FIG. 1C.
U.S. Pat. No. 6,607,977 describes a process that address in-part the poor coverage observed with a PVD deposited barrier layer at the side walls near the bottom of the via. FIG. 2A is a cross-sectional view after depositing a PVD barrier 26 over a patterned dielectric 21. Again, there is poor or non-conformal coverage at site 27. A second deposition process is then used to simultaneously etch the barrier material 26 that deposited at the bottom of via 25 while at the same time deposit a second barrier material. This second deposition process is said to provide enhanced coverage at the lower side walls of the via, i.e. site 27, as shown in FIG. 2B. However, one disadvantage with such a process is that the amount of material that is etched and redeposited is limited by the amount of barrier material that originally deposited at the via bottom.
However, as the market demand continues for smaller and smaller circuit dimension, PVD's limitation in conformal step coverage is a problem that needs to be addressed. In a dual-damascene BEOL process scheme, a problem is the resulting poor barrier coverage at the bottom of via sidewalls. This in turn can degrade circuit reliability over time. A similar problem is observed in a BEOL single-damascene integration scheme when the wiring aspect ratio is greater than 5.